1. Field of the Invention
The present invention relates to fixed and variable latency peripherals. More specifically, the present invention relates to methods and apparatus for generating control and routing lines to allow primary and secondary components to interact using fixed or variable latency.
2. Description of Related Art
Conventional programmable chip systems often include a variety of primary components and secondary components, such as processors, memory, parallel input/output interfaces, timers, etc. The primary and secondary components can interact using a variety of mechanisms. In one example, secondary components are fixed latency peripherals. The secondary components are configured to return data requested by a primary component within a fixed number of clock cycles.
Some secondary components, such as memory, can return data at different rates. Without variable latency support, efficiency is decreased as only a single read access can be pending at any given time. However, with variable latency, the throughput can increase to one access per clock cycle.
However, techniques and mechanisms for providing fixed and variable latency support for programmable chips are limited. Consequently, it is therefore desirable to provide improved methods and apparatus for supporting fixed and variable latency components. In one example, it is desirable to provide logic and circuitry to interconnect primary and secondary component using robust and flexible mechanisms.